Charge trapping, non-volatile memory cells are known in the art. Nitride read only memory (NROM) cells are based on a charge trapping material that is capable of storing one or more bits of data within a single cell. A typical use of NROM devices is to store at least two bits of data within one cell, where the bits are stored in physically separated charge storage areas, one on either side of the cell. Each storage area can be operated in a single-level or in a multi-level mode.
The cells are typically formed into memory arrays, formed of rows and columns of memory cells electrically connected to word lines (e.g. rows of the array) and bit lines (columns). Reference is now made to FIG. 1, which illustrates a typical example of a row of a prior art array of NROM cells.
In this row, as in the other rows of the array, each memory cell 10 is connected to a word line WL and to two local bit lines LBL(j), where each local bit line serves two neighboring columns. To program a cell, for example, cell 10A, a high voltage (VWL) is provided on word line WL, to activate the row of cells. A programming voltage (VP) is provided on one of the local bit lines, for example LBL3, surrounding cell 10A and a close to ground voltage (GND) is provided on the other local bit line, such as LBL4. The remaining local bit lines in the vicinity of cell 10A are maintained floating. Due to the combination of high voltage VWL at its gate G and programming voltage VP at its drain D, the left side storage area of cell 10A will become programmed.
During such a programming operation, the floating local bit lines near local bit line LBL3 also charge up. Cells 10B and 10C act as transfer devices, transferring charge to local bit lines LBL2 and LBL1 which, in turn, charge up, and their voltages follow that of LBL3. The longer the programming pulse is, the more the floating local bit lines will be charged up. This charging current flowing through the memory cells in the vicinity of the cell being programmed is sometimes referred as a “leak current” (Ileak) or as the “Virtual Ground pipe current” (IVGpipe). This pipe current does not cause programming of the cells in the pipe due to the low drain-source voltage across those cells. However, very unfortunately, this unnecessary charging of local bit lines is not required for programming cell 10A and wastes unnecessary power. Furthermore, since IVGpipe is driven from the bit line voltage supply (VP), which is typically generated by a charge pump, and since the charge pump efficiency is relatively low, the power penalty caused by IVGpipe is very significant.
A similar “pipe effect” occurs on the other side of cell 10A, i.e. the floating local bit lines LBL5, LBL6, etc., also follow local bit line LBL4. However, since local bit line LBL4 is driven to a close to ground level, these local bit lines are not significantly charged and thus, the virtual ground pipe effect generally refers only to the virtual ground pipe at the high voltage side.
To reduce the charging current IVGpipe, the virtual ground pipe may be shortened via isolation columns 12 which may “slice” the rows of the array into slices having a pre-defined number of columns. Isolation columns 12 stop the propagation of the charging current IVGpipe, and reduce the amount of capacitance (of the local bit lines) unnecessarily charged during a programming pulse. Of course, such slicing increases the total die area due to the additional isolation columns 12.
An additional method to minimize IVGpipe is to reduce the capacitance of the local bit lines by segmenting them. In this method, the virtual ground array is segmented into multiple physical sectors (one of which is shown in FIG. 2, to which reference is now made), which can be separately activated.
The architecture of FIG. 2 also includes global bit lines (GBLs), which enable access to memory cells of different physical sectors. Select transistor 14 connect selected physical sectors to the global bit lines. Groups of select transistors 14 are activated by select lines SELk. Typically, the select transistors 14 of a group are spread apart in the array.
In the specific array configuration shown in FIG. 2, one set of select transistors 14 connects to the even-numbered local bit lines, at one end of the local bit lines, while another set of transistors connects to the odd-numbered local bit lines, at a second end of the local bit lines. When programming a bit of a memory cell, for example, the right storage area of memory cell 11, its word line, such as WL(i), is activated by an X decoder 16, power is provided, by a Y unit 18, on global bit line GBL(N) and Y unit 18 connects global bit line GBL(N+1) to ground. Y unit 18 typically may also decode the address of memory cell 11 and from the result, may activate the selected global bit lines GBL and may instruct XDEC 16 as to which select transistors SEL to activate.
Select lines SEL4 and SEL5 are activated respectively to connect global bit line GBL(N+1) to LBLa and LBLb to global bit line GBL(N). Thus, as shown with the arrows, programming current Ipgm flows from global bit line GBL(N), through select transistor SEL5 to local bit line LBLb, through activated memory cell 11, to local bit line LBLa, to select transistor SEL4 and, from there, to global bit line GBL(N+1) connected to ground. Of course, while applying a programming pulse to the right storage area of cell 11, the local bit lines to the right of LBLb, i.e. the virtual ground pipe to the right of cell 11, are charged, unnecessarily wasting power.
While the virtual ground array segmentation of FIG. 2 may reduce local bit line capacitance and thus, the power waste, it requires select transistors (for segmentation) and therefore has a significant die area penalty.
Usually, when programming a non-volatile memory array, more than a single cell is programmed at a time. The number of cells being programmed in parallel typically depends on the device specifications (e.g. programming rate, current consumption, etc.). In general, the cells being programmed in parallel share the same word line and the same physical sector, and are typically located in different virtual ground slices. Each of the cells being programmed in parallel suffers from the virtual ground pipe effect, and therefore, the larger the number of cells being programmed, the larger the wasted power is.
It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.